Perpendicularly magnetized magnetic tunnel junctions (p-MTJs) are a major emerging technology for use in embedded magnetic random access memory (MRAM) applications, and in standalone MRAM applications. STT-MRAM is a p-MTJ technology using spin-torque for writing of memory bits that was described by C. Slonezewski in “Current driven excitation of magnetic multilayers”, J. Magn. Magn. Mater. V 159, L1-L7 (1996). P-MTJ technologies are highly competitive with existing semiconductor memory technologies such as SRAM, DRAM, and flash.
P-MTJs have a general structure wherein an insulating tunnel barrier is sandwiched between two magnetic layers. One of the magnetic layers is called the reference layer and has a magnetization fixed in an out-of-plane direction in the (+y) direction, for example, when the plane of the magnetic layer is formed along the x-axis and z-axis directions. The second magnetic layer called the free layer also has an out-of-plane magnetization with a direction that is free to be either parallel in a (+y) direction (P state) or anti-parallel in a (−y) direction (AP state). The difference in resistance between the P state (Rp) and AP state (Rap) can be characterized by the equation (Rap-Rp)/Rp that is also known as DRR or the magnetoresistive (MR) ratio. It is important for p-MTJ devices to have a large DRR value since this property is directly related to the read margin for the memory bit, or the ease of differentiating between the P state and AP state (0 or 1 bits).
To compete with high speed embedded RAM technologies, patterned p-MTJs in the form of nanopillars must be fabricated into high density arrays with single bits that can be written at high speed (<100 ns) at low writing currents. An encapsulation layer made of a dielectric material is typically deposited to fill gaps between adjacent p-MTJ nanopillars to electrically insulate the devices. To achieve the goal of low writing currents, total volume “V” in the free layer must be reduced, which is most easily achieved by reducing the physical dimensions of the p-MTJ. One or both of the x-axis and z-axis dimensions may be reduced when a thickness of each p-MTJ layer is in the y-axis direction. Moreover, the thickness of the free layer may be reduced to shrink V. However, as the physical dimensions decrease, the effect of current conductance through “edge” or sidewall regions of the p-MTJ nanopillar becomes more pronounced. These edge regions are of particular importance as crystal structure damage from etching, encapsulation, and annealing processes may greatly affect critical device properties such as free layer coercivity (Hc), DRR, and resistance-area product (RA).
For embedded MRAM designs, p-MTJ devices are subject to 400° C. annealing for a plurality of hours due to Complementary Metal Oxide Semiconductor (CMOS) back-end-of-line (BEOL) processes. Therefore, thermal stability of the encapsulation layer/p-MTJ interface is of extreme importance, especially for devices with a critical dimension proximate to 100 nm or less. Furthermore, a process flow for etching MTJ sidewalls is desired that substantially reduces sidewall damage for devices with a diameter or critical dimension (CD) around 45 nm or less where a significant portion of device current flows near the encapsulation layer/p-MTJ interface. This interface may be modified by exposure to reactive species during etching to form the p-MTJ sidewalls, and during deposition of the encapsulation layer. Furthermore, any process steps performed between p-MTJ etching and encapsulation may influence the integrity of the p-MTJ sidewalls, as well as the crystal structure and chemical composition of films that constitute the p-MTJ nanopillar thereby enhancing or degrading overall p-MTJ bit performance.
In order for p-MTJs to be more competitive with competing memory technologies, DRR must be substantially improved while maintaining the other critical device properties during BEOL processing.